module rt71_line_buffer_ctrl(
dclk,
reset_n,

in_end_frame,
in_cs_desync_rst,                   //??
in_first_de_enable,                 //?? rt8
in_xdio, 

in_res,                             //resolution(max=15 choice)
in_hact,                            //resolution(max=5120)
port_num,                           //port num (max=16)   
sd_ch_num,                          //SD_CH 11 bit
nml_cnt_stop,                       //(sd_ch)/12 take quotient, need excel to calculate                 
dummy_num_head,                     //(max=15) dummy number at head of line

pix_sft_en,
sft_dir,
data_rvs,
in_isp_en, 

in_nml_de,
in_nml_r1,
in_nml_g1,
in_nml_b1,
in_nml_r2,
in_nml_g2,
in_nml_b2,
in_nml_r3,
in_nml_g3,
in_nml_b3,
in_nml_r4,
in_nml_g4,
in_nml_b4,

// out_sram0_lb1_rdata, out_sram1_lb1_rdata, out_sram2_lb1_rdata, out_sram3_lb1_rdata,  //dout
// out_sram0_lb2_rdata, out_sram1_lb2_rdata, out_sram2_lb2_rdata, out_sram3_lb2_rdata, 
// out_sram0_lb3_rdata, out_sram1_lb3_rdata, out_sram2_lb3_rdata, out_sram3_lb3_rdata, 
// out_sram0_lb4_rdata, out_sram1_lb4_rdata, out_sram2_lb4_rdata, out_sram3_lb4_rdata,

out_sram0_lb1_wr, out_sram1_lb1_wr, out_sram2_lb1_wr, out_sram3_lb1_wr,              //wen = out_sram?_lb?_wr 
out_sram0_lb2_wr, out_sram1_lb2_wr, out_sram2_lb2_wr, out_sram3_lb2_wr,
out_sram0_lb3_wr, out_sram1_lb3_wr, out_sram2_lb3_wr, out_sram3_lb3_wr,
out_sram0_lb4_wr, out_sram1_lb4_wr, out_sram2_lb4_wr, out_sram3_lb4_wr,

out_sram0_lb1_rd, out_sram1_lb1_rd, out_sram2_lb1_rd, out_sram3_lb1_rd,               //cen = (out_sram?_lb?_wr|out_sram?_lb?_rd_t)
out_sram0_lb2_rd, out_sram1_lb2_rd, out_sram2_lb2_rd, out_sram3_lb2_rd,
out_sram0_lb3_rd, out_sram1_lb3_rd, out_sram2_lb3_rd, out_sram3_lb3_rd,
out_sram0_lb4_rd, out_sram1_lb4_rd, out_sram2_lb4_rd, out_sram3_lb4_rd,

out_sram0_lb1_addr, out_sram1_lb1_addr, out_sram2_lb1_addr, out_sram3_lb1_addr,       //addr_insram  (max=1280+11,11bit)
out_sram0_lb2_addr, out_sram1_lb2_addr, out_sram2_lb2_addr, out_sram3_lb2_addr,    
out_sram0_lb3_addr, out_sram1_lb3_addr, out_sram2_lb3_addr, out_sram3_lb3_addr,    
out_sram0_lb4_addr, out_sram1_lb4_addr, out_sram2_lb4_addr, out_sram3_lb4_addr,  

r_out_sram0_lb1_addr, r_out_sram0_lb2_addr, r_out_sram0_lb3_addr, r_out_sram0_lb4_addr,  //addr_outsram
r_out_sram1_lb1_addr, r_out_sram1_lb2_addr, r_out_sram1_lb3_addr, r_out_sram1_lb4_addr,
r_out_sram2_lb1_addr, r_out_sram2_lb2_addr, r_out_sram2_lb3_addr, r_out_sram2_lb4_addr,
r_out_sram3_lb1_addr, r_out_sram3_lb2_addr, r_out_sram3_lb3_addr, r_out_sram3_lb4_addr,
  
out_sram0_lb1_wdata, out_sram1_lb1_wdata, out_sram2_lb1_wdata, out_sram3_lb1_wdata,   //din 
out_sram0_lb2_wdata, out_sram1_lb2_wdata, out_sram2_lb2_wdata, out_sram3_lb2_wdata,
out_sram0_lb3_wdata, out_sram1_lb3_wdata, out_sram2_lb3_wdata, out_sram3_lb3_wdata,
out_sram0_lb4_wdata, out_sram1_lb4_wdata, out_sram2_lb4_wdata, out_sram3_lb4_wdata

);

//Din
input dclk;
input reset_n;

input in_end_frame;
input in_cs_desync_rst;                       //??
input in_first_de_enable;                     //?? rt8
input in_xdio;                                
                                              
input [3:0] in_res;                           //resolution(max=15 choice)
input [10:0] in_hact;                         //resolution(max=5120/4)
input [4:0] port_num;                         //port num (max=16)   
input [10:0] sd_ch_num;                       //SD_CH 11 bit
input [6:0] nml_cnt_stop;                     //(sd_ch)/12 take quotient, need excel to calculate                
input [3:0] dummy_num_head;                   //(max=15) dummy number at head of line

input sft_dir;

input pix_sft_en;
input data_rvs;
input in_isp_en; 

input       in_nml_de;
input [9:0] in_nml_r1;
input [9:0] in_nml_g1;
input [9:0] in_nml_b1;
input [9:0] in_nml_r2;
input [9:0] in_nml_g2;
input [9:0] in_nml_b2;
input [9:0] in_nml_r3;
input [9:0] in_nml_g3;
input [9:0] in_nml_b3;
input [9:0] in_nml_r4;
input [9:0] in_nml_g4;
input [9:0] in_nml_b4;

// output [29:0] out_sram0_lb1_rdata, out_sram1_lb1_rdata, out_sram2_lb1_rdata, out_sram3_lb1_rdata;      //dout
// output [29:0] out_sram0_lb2_rdata, out_sram1_lb2_rdata, out_sram2_lb2_rdata, out_sram3_lb2_rdata; 
// output [29:0] out_sram0_lb3_rdata, out_sram1_lb3_rdata, out_sram2_lb3_rdata, out_sram3_lb3_rda//ta; 
// output [29:0] out_sram0_lb4_rdata, out_sram1_lb4_rdata, out_sram2_lb4_rdata, out_sram3_lb4_rdata;

output out_sram0_lb1_wr, out_sram1_lb1_wr, out_sram2_lb1_wr, out_sram3_lb1_wr;                    //wen = out_sram?_lb?_wr 
output out_sram0_lb2_wr, out_sram1_lb2_wr, out_sram2_lb2_wr, out_sram3_lb2_wr;
output out_sram0_lb3_wr, out_sram1_lb3_wr, out_sram2_lb3_wr, out_sram3_lb3_wr;
output out_sram0_lb4_wr, out_sram1_lb4_wr, out_sram2_lb4_wr, out_sram3_lb4_wr;

output out_sram0_lb1_rd, out_sram1_lb1_rd, out_sram2_lb1_rd, out_sram3_lb1_rd;                    //cen = (out_sram?_lb?_wr|out_sram?_lb?_rd_t)
output out_sram0_lb2_rd, out_sram1_lb2_rd, out_sram2_lb2_rd, out_sram3_lb2_rd;
output out_sram0_lb3_rd, out_sram1_lb3_rd, out_sram2_lb3_rd, out_sram3_lb3_rd;
output out_sram0_lb4_rd, out_sram1_lb4_rd, out_sram2_lb4_rd, out_sram3_lb4_rd;

output [10:0] out_sram0_lb1_addr, out_sram1_lb1_addr, out_sram2_lb1_addr, out_sram3_lb1_addr;     //addr (max=1280+11,11bit)
output [10:0] out_sram0_lb2_addr, out_sram1_lb2_addr, out_sram2_lb2_addr, out_sram3_lb2_addr;    
output [10:0] out_sram0_lb3_addr, out_sram1_lb3_addr, out_sram2_lb3_addr, out_sram3_lb3_addr;    
output [10:0] out_sram0_lb4_addr, out_sram1_lb4_addr, out_sram2_lb4_addr, out_sram3_lb4_addr; 

output [10:0] r_out_sram0_lb1_addr, r_out_sram0_lb2_addr, r_out_sram0_lb3_addr, r_out_sram0_lb4_addr;
output [10:0] r_out_sram1_lb1_addr, r_out_sram1_lb2_addr, r_out_sram1_lb3_addr, r_out_sram1_lb4_addr;
output [10:0] r_out_sram2_lb1_addr, r_out_sram2_lb2_addr, r_out_sram2_lb3_addr, r_out_sram2_lb4_addr; 
output [10:0] r_out_sram3_lb1_addr, r_out_sram3_lb2_addr, r_out_sram3_lb3_addr, r_out_sram3_lb4_addr;  

output [29:0] out_sram0_lb1_wdata, out_sram1_lb1_wdata, out_sram2_lb1_wdata, out_sram3_lb1_wdata;  //din
output [29:0] out_sram0_lb2_wdata, out_sram1_lb2_wdata, out_sram2_lb2_wdata, out_sram3_lb2_wdata;
output [29:0] out_sram0_lb3_wdata, out_sram1_lb3_wdata, out_sram2_lb3_wdata, out_sram3_lb3_wdata;
output [29:0] out_sram0_lb4_wdata, out_sram1_lb4_wdata, out_sram2_lb4_wdata, out_sram3_lb4_wdata;

// output out_rd_sram0;
// output out_rd_sram1;
// output out_rd_sram2;
// output out_rd_sram3;


//Data delay
reg [9:0] r1_d1, g1_d1, b1_d1, r1_d2, g1_d2, b1_d2;                  
reg [9:0] r2_d1, g2_d1, b2_d1, r2_d2, g2_d2, b2_d2;                 
reg [9:0] r3_d1, g3_d1, b3_d1, r3_d2, g3_d2, b3_d2;                 
reg [9:0] r4_d1, g4_d1, b4_d1, r4_d2, g4_d2, b4_d2;                 
always @(posedge dclk or negedge reset_n)
begin
 if (!reset_n)
 begin
    r1_d1 <= 10'd0; 
    g1_d1 <= 10'd0; 
    b1_d1 <= 10'd0; 
    r2_d1 <= 10'd0; 
    g2_d1 <= 10'd0; 
    b2_d1 <= 10'd0;  
    r3_d1 <= 10'd0; 
    g3_d1 <= 10'd0; 
    b3_d1 <= 10'd0; 
    r4_d1 <= 10'd0; 
    g4_d1 <= 10'd0; 
    b4_d1 <= 10'd0;
    r1_d2 <= 10'd0; 
    g1_d2 <= 10'd0; 
    b1_d2 <= 10'd0; 
    r2_d2 <= 10'd0; 
    g2_d2 <= 10'd0; 
    b2_d2 <= 10'd0;  
    r3_d2 <= 10'd0; 
    g3_d2 <= 10'd0; 
    b3_d2 <= 10'd0; 
    r4_d2 <= 10'd0; 
    g4_d2 <= 10'd0; 
    b4_d2 <= 10'd0;
 end else begin
    r1_d1 <= in_nml_r1;
    g1_d1 <= in_nml_g1;
    b1_d1 <= in_nml_b1;
    r2_d1 <= in_nml_r2;
    g2_d1 <= in_nml_g2;
    b2_d1 <= in_nml_b2;
    r3_d1 <= in_nml_r3;
    g3_d1 <= in_nml_g3;
    b3_d1 <= in_nml_b3;
    r4_d1 <= in_nml_r4;
    g4_d1 <= in_nml_g4;
    b4_d1 <= in_nml_b4;
        r1_d2 <= r1_d1;
    g1_d2 <= g1_d1;
    b1_d2 <= b1_d1;
    r2_d2 <= r2_d1;
    g2_d2 <= g2_d1;
    b2_d2 <= b2_d1;
    r3_d2 <= r3_d1;
    g3_d2 <= g3_d1;
    b3_d2 <= b3_d1;
    r4_d2 <= r4_d1;
    g4_d2 <= g4_d1;
    b4_d2 <= b4_d1;
 end
end

//DE delay
reg xdio_d1, xdio_d2;
reg xdio_d3, xdio_d4;
reg xdio_d5, xdio_d6, xdio_d7, xdio_d8;
reg nml_de_d1, nml_de_d2, nml_de_d3;
reg endframe_d1;
always @( posedge dclk or negedge reset_n )
begin
  if (!reset_n)
  begin
    xdio_d1 <= 1'd0;
    xdio_d2 <= 1'd0;
    xdio_d3 <= 1'd0;  
    xdio_d4 <= 1'd0;      
    xdio_d5 <= 1'd0;      
    xdio_d6 <= 1'd0;
    xdio_d7 <= 1'b0;
    xdio_d8 <= 1'b0;
    nml_de_d1   <= 1'd0;  
    nml_de_d2   <= 1'd0;
    nml_de_d3   <= 1'b0;
    endframe_d1 <= 1'b0;    
  end else begin
    xdio_d1 <= in_xdio;
    xdio_d2 <= xdio_d1;
    xdio_d3 <= xdio_d2; 
    xdio_d4 <= xdio_d3;      
    xdio_d5 <= xdio_d4;      
    xdio_d6 <= xdio_d5;
    xdio_d7 <= xdio_d6;     
    xdio_d8 <= xdio_d7;
    nml_de_d1   <= in_nml_de;
    nml_de_d2   <= nml_de_d1;
    nml_de_d3   <= nml_de_d2;
    endframe_d1 <= in_end_frame;
  end
end

wire endframe_pe = (in_end_frame & ~endframe_d1);    //(| in_cs_desync_rst)
wire nml_de_pe  = in_nml_de & (~nml_de_d1);
wire nml_de_ne  = (~in_nml_de) & nml_de_d1;




//LB counter: count the referance signal of  "sram_addr & LB circle"
wire sd_div4 = (sd_ch_num[1:0] == 2'd0);         //SD_CH/4 =\=0, special case

// 1. port_num setting
reg port_4n;                                    //port_num/4=0
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    port_4n <= 1'd0;
  end else 
    port_4n <= (port_num[1:0] == 2'd0);                       
end

reg port_4n_add2;                               //port_num/(4n+2)=0
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    port_4n_add2 <= 1'd0;
  end else 
    port_4n_add2 <= (port_num[1:0] == 2'd2);                        
end

reg port_odd;                                   //port_num=odd
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    port_odd <= 1'd0;
  end else 
    port_odd <= (port_num[1:0] == 2'd1);                        
end

reg [7:0] lb_cnt_stop_temp;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    lb_cnt_stop_temp <= 8'd0;
  end else begin
    if( sd_div4 )
       lb_cnt_stop_temp <= nml_cnt_stop;
    else
       lb_cnt_stop_temp <= nml_cnt_stop + nml_cnt_stop;
  end
end

// 2. line buffer counter
wire lb_cnt_eq_stop;
reg [7:0] lb_cnt_stop;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    lb_cnt_stop <= 8'd0;
  end 
  else if( ~sft_dir )
       lb_cnt_stop <= lb_cnt_stop_temp;                //sft_dir=0, stop doesn't need to adjust
       else if ( nml_de_pe )                  
            lb_cnt_stop <= lb_cnt_stop_temp + 8'd1;    //sft_dir=1,& lb_cnt_stop_temp+1 in every line first LB cycle           
                        else if ( lb_cnt_eq_stop )
                 lb_cnt_stop <= lb_cnt_stop_temp + 8'd1;
                             else
                                 lb_cnt_stop <= lb_cnt_stop;
end


wire lb_cnt_eq_stop_p1; 
reg [7:0] lb_cnt;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    lb_cnt <= 8'd0;
  end 
  else if( nml_de_pe )
    lb_cnt <= {6'd0,dummy_num_head[3:2]};            
       else if ( lb_cnt_eq_stop )                  
            lb_cnt <= 8'd1;  
            else 
            lb_cnt <= lb_cnt + 8'd1;
end
assign lb_cnt_eq_stop = (lb_cnt == lb_cnt_stop);
assign lb_cnt_eq_stop_p1 = (lb_cnt == (lb_cnt_stop - 7'd1));      

 

// 3.line buffer change 

reg [4:0] lb_change_stop;                                       //port_num=4n case -> lb_change_stop=4; (4n+2)&odd case -> lb_change_stop=port num; 
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
    lb_change_stop <= 5'd0;
  else 
    lb_change_stop <= port_4n ? 5'd3 : (port_num - 5'd1);                        
end

wire addr_mid_stop =  (lb_cnt == nml_cnt_stop);                //SD_ch=12n case, addr_mid_stop = lb_cnt_eq_stop
wire lb_change_add = lb_cnt_eq_stop | addr_mid_stop;

wire lb_change_reset;
wire lb_change_reset_p1;
reg [3:0] lb_change;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
    lb_change <= 4'd0;
  else 
    lb_change <= nml_de_pe ? 4'd0 : (lb_change_reset ? 4'd0 : (lb_change_add ? (lb_change + 4'd1) : lb_change));                     
end
assign lb_change_reset = (lb_change == lb_change_stop) & (lb_cnt_eq_stop);
assign lb_change_reset_p1 = (lb_change == lb_change_stop) & (lb_cnt_eq_stop_p1);


//for port_num=(4n+2)&odd case: line buffer change_pre

// 1. line buffer counter_pre
//    wire lb_cnt_eq_stop_p1 = (lb_cnt == lb_cnt_stop - 7'd1);  
   
// 2. line buffer change_pre 
wire addr_mid_stop_p1 =  (lb_cnt == (nml_cnt_stop - 7'd1));    
wire lb_change_add_p1 = lb_cnt_eq_stop_p1 | addr_mid_stop_p1;

// wire lb_change_reset_p1;
reg [3:0] lb_change_p1;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    lb_change_p1 <= 4'd0;
  end else 
    lb_change_p1 <= nml_de_pe ? 4'd0 : (lb_change_reset_p1 ? 4'd0 : (lb_change_add_p1 ? (lb_change + 4'd1) : lb_change_p1));                     
end
// assign lb_change_reset_p1 = (lb_change_p1 == lb_change_stop) & (lb_cnt_eq_stop_p1);   //lb change stop是沒有變的





//Address Counter

wire [2:0] addr_star_dif = port_num[4:2];                     // port_num/4 to count differencee (4n case)
//addr(1-4)_star
reg [3:0] addr1_start, addr2_start, addr3_start, addr4_start;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    addr1_start <= 4'd0; 
    addr2_start <= 4'd0; 
    addr3_start <= 4'd0; 
    addr4_start <= 4'd0;
  end else if ( port_4n )
      begin addr1_start <= 4'd0;                                                     //port_num=4n
            addr2_start <= addr_star_dif;
            addr3_start <= addr2_start + addr_star_dif;
            addr4_start <= addr3_start + addr_star_dif; end     
      else if (port_4n_add2)                                                             //port_num=6
           casex ( lb_change_p1[2:0] )
           3'b00x:begin
                  addr1_start <= 4'd0; addr2_start <= 4'd1; addr3_start <= 4'd3; addr4_start <= 4'd4; end    
           3'b01x:begin
                  addr1_start <= 4'd0; addr2_start <= 4'd2; addr3_start <= 4'd3; addr4_start <= 4'd5; end
           3'b10x:begin
                  addr1_start <= 4'd1; addr2_start <= 4'd2; addr3_start <= 4'd4; addr4_start <= 4'd5; end   //IF port_num=10, 再往上擴充
           endcase
           else begin
               addr1_start <= 4'd0; addr2_start <= 4'd0; addr3_start <= 4'd0; addr4_start <= 4'd0; end
end

//addr_start_offset
reg [6:0] addr_start_offset_temp;                           //addr offset(by dummy num), max=48 (muti-cycle constrain)
wire [6:0] test = dummy_num_head[3:2]*port_num[4:0];
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    addr_start_offset_temp <= 7'd0;
  end else 
    addr_start_offset_temp <= test;                     
end



reg [6:0] addr_start_offset;                                               //max=64
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    addr_start_offset <= 7'd0;
  end else begin 
  if( sft_dir )
      addr_start_offset <= addr_start_offset_temp;            
  else 
      addr_start_offset <= (addr_start_offset_temp + port_num);
  end
end

//addr_star(1-4) = addr(1-4)_star + addr_start_offset
reg [6:0] addr_start1_1st, addr_start2_1st, addr_start3_1st, addr_start4_1st;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
   addr_start1_1st <= 7'd0;              
   addr_start2_1st <= 7'd0;
   addr_start3_1st <= 7'd0;
   addr_start4_1st <= 7'd0;
  end else begin
      addr_start1_1st <= addr1_start + addr_start_offset;    //max=76, for 1st LB cycle
      addr_start2_1st <= addr2_start + addr_start_offset;
      addr_start3_1st <= addr3_start + addr_start_offset;
      addr_start4_1st <= addr4_start + addr_start_offset;  end
end

reg [4:0] addr_start1, addr_start2, addr_start3, addr_start4;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
   addr_start1 <= 5'd0;              
   addr_start2 <= 5'd0;
   addr_start3 <= 5'd0;
   addr_start4 <= 5'd0;
  end else if ( nml_de_pe ) begin
      addr_start1 <= addr1_start + port_num;    //max=31, for LB cycle of 2nd behind 2nd, and everytime of lb_change_reset, addr_start(1-4) need to +1
      addr_start2 <= addr2_start + port_num;
      addr_start3 <= addr3_start + port_num;
      addr_start4 <= addr4_start + port_num;  
          end else if ( lb_change_reset_p1 ) begin
              addr_start1 <= addr_start1 + 5'd1;            
              addr_start2 <= addr_start2 + 5'd1;
              addr_start3 <= addr_start3 + 5'd1;
              addr_start4 <= addr_start4 + 5'd1;   end
                  else begin
                  addr_start1 <= addr_start1;            
                  addr_start2 <= addr_start2;
                  addr_start3 <= addr_start3;
                  addr_start4 <= addr_start4;   end
end

// addr_stop
wire addr_stop = lb_cnt_eq_stop; 

reg addr_mid_stop_d1; 
reg addr_mid_stop_d2;
always @( posedge dclk or negedge reset_n )
begin
  if (!reset_n)
  begin
    addr_mid_stop_d1 <= 1'd0;
    addr_mid_stop_d2 <= 1'd0;    
  end else begin
    addr_mid_stop_d1 <= addr_mid_stop;
    addr_mid_stop_d2 <= addr_mid_stop_d1;  end
end


 

// addr_cnt
reg [10:0] addr_cnt1,addr_cnt2;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
   addr_cnt1 <= 11'd0;              
   addr_cnt2 <= 11'd0;
  end else if ( nml_de_pe ) begin
      addr_cnt1 <= addr_start1_1st;              
      addr_cnt2 <= addr_start2_1st;
          end else if ( addr_stop ) begin
              addr_cnt1 <= addr_start1;            
              addr_cnt2 <= addr_start2;  end
                       else if ( sd_div4 )begin
                       addr_cnt1 <= addr_cnt1 + port_num;
                       addr_cnt2 <= addr_cnt2 + port_num;  end
                                else if ( addr_mid_stop_d1 )begin
                                addr_cnt1 <= addr_start3;
                                addr_cnt2 <= addr_start4;  end
                                     else begin
                                     addr_cnt1 <= addr_cnt1 + port_num;
                                     addr_cnt2 <= addr_cnt2 + port_num;  end
end


reg [10:0] addr_cnt3,addr_cnt4;
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
   addr_cnt3 <= 11'd0;              
   addr_cnt4 <= 11'd0;
  end else if ( nml_de_pe ) begin
      addr_cnt3 <= addr_start3_1st;              
      addr_cnt4 <= addr_start4_1st;
          end else if ( addr_stop ) begin
              addr_cnt3 <= addr_start3;            
              addr_cnt4 <= addr_start4;  end
                       else if ( addr_mid_stop ) begin     
                       addr_cnt3 <= addr_start1;
                       addr_cnt4 <= addr_start2;  end
                            else begin 
                            addr_cnt3 <= addr_cnt3 + port_num;
                            addr_cnt4 <= addr_cnt4 + port_num;  end
end








// signal to sram

//write & read line counter 
reg [1:0] wr_line_no;                                //reference nml_de_pe 
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    wr_line_no <= 2'd3;
  end else begin
    if( endframe_pe )
       wr_line_no <= 2'd3;
    else if ( nml_de_pe ) 
         wr_line_no <= wr_line_no + 2'd1;
    else if (nml_de_ne & in_end_frame & ~in_first_de_enable)    //for glitch in end_frame reset 
         wr_line_no <= 2'd3;        
    else
       wr_line_no <= wr_line_no;
  end
end

reg [1:0] rd_line_no;                                 //reference xdio_d1
always @(posedge dclk or negedge reset_n)
begin
  if (!reset_n)
  begin
    rd_line_no <= 2'd3;
  end else if( endframe_pe )
       rd_line_no <= 2'd3;
           else if ( xdio_d1 )
                rd_line_no <= rd_line_no + 2'd1;
                else
                rd_line_no <= rd_line_no;
end

wire sram_wr_flag = nml_de_d1 | nml_de_d3;                  //de_d3??      
wire wr_sram0 = (wr_line_no == 2'd0) & sram_wr_flag; 
wire wr_sram1 = (wr_line_no == 2'd1) & sram_wr_flag; 
wire wr_sram2 = (wr_line_no == 2'd2) & sram_wr_flag; 
wire wr_sram3 = (wr_line_no == 2'd3) & sram_wr_flag; 

wire out_rd_sram0 = (rd_line_no == 2'd0); 
wire out_rd_sram1 = (rd_line_no == 2'd1); 
wire out_rd_sram2 = (rd_line_no == 2'd2); 
wire out_rd_sram3 = (rd_line_no == 2'd3); 

//write (wen)
wire out_sram0_lb1_wr = wr_sram0;                     //1st line
wire out_sram0_lb2_wr = wr_sram0;
wire out_sram0_lb3_wr = wr_sram0;
wire out_sram0_lb4_wr = wr_sram0;

wire out_sram1_lb1_wr = wr_sram1;                     //2nd line
wire out_sram1_lb2_wr = wr_sram1;
wire out_sram1_lb3_wr = wr_sram1;
wire out_sram1_lb4_wr = wr_sram1;

wire out_sram2_lb1_wr = wr_sram2;                     //3rd line
wire out_sram2_lb2_wr = wr_sram2;
wire out_sram2_lb3_wr = wr_sram2;
wire out_sram2_lb4_wr = wr_sram2;

wire out_sram3_lb1_wr = wr_sram3;                     //4th line
wire out_sram3_lb2_wr = wr_sram3;
wire out_sram3_lb3_wr = wr_sram3;
wire out_sram3_lb4_wr = wr_sram3;

// read (cen)
wire out_sram0_lb1_rd = (out_rd_sram0 | wr_sram0);     //1st line
wire out_sram0_lb2_rd = (out_rd_sram0 | wr_sram0);
wire out_sram0_lb3_rd = (out_rd_sram0 | wr_sram0);
wire out_sram0_lb4_rd = (out_rd_sram0 | wr_sram0);

wire out_sram1_lb1_rd = (out_rd_sram1 | wr_sram1);     //2nd line
wire out_sram1_lb2_rd = (out_rd_sram1 | wr_sram1); 
wire out_sram1_lb3_rd = (out_rd_sram1 | wr_sram1);
wire out_sram1_lb4_rd = (out_rd_sram1 | wr_sram1); 

wire out_sram2_lb1_rd = (out_rd_sram2 | wr_sram2);     //3rd line
wire out_sram2_lb2_rd = (out_rd_sram2 | wr_sram2); 
wire out_sram2_lb3_rd = (out_rd_sram2 | wr_sram2);
wire out_sram2_lb4_rd = (out_rd_sram2 | wr_sram2); 

wire out_sram3_lb1_rd = (out_rd_sram3 | wr_sram3);     //4th line
wire out_sram3_lb2_rd = (out_rd_sram3 | wr_sram3); 
wire out_sram3_lb3_rd = (out_rd_sram3 | wr_sram3);
wire out_sram3_lb4_rd = (out_rd_sram3 | wr_sram3); 


//1st set SRAM
reg [10:0] out_sram0_lb1_addr;
reg [10:0] out_sram0_lb2_addr;
reg [10:0] out_sram0_lb3_addr;
reg [10:0] out_sram0_lb4_addr;
reg [29:0] out_sram0_lb1_wdata, out_sram0_lb2_wdata, out_sram0_lb3_wdata, out_sram0_lb4_wdata;
wire dummy_head_or =  dummy_num_head[3] | dummy_num_head[2];     //OR MSB 2bit to reduce case size
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  begin
     out_sram0_lb1_addr <= 11'd0;
     out_sram0_lb2_addr <= 11'd0;
     out_sram0_lb3_addr <= 11'd0;
     out_sram0_lb4_addr <= 11'd0;
     out_sram0_lb1_wdata <= 30'd0;
     out_sram0_lb2_wdata <= 30'd0;
     out_sram0_lb3_wdata <= 30'd0;
     out_sram0_lb4_wdata <= 30'd0;
  end else if ( wr_sram0 ) begin
            casex ({dummy_head_or, dummy_num_head[1:0]})               
        3'b000:begin                                               //Dummy head=0     
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                       out_sram0_lb1_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram0_lb1_addr <= addr_cnt1;
                       out_sram0_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram0_lb2_addr <= addr_cnt2;
                       out_sram0_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram0_lb3_addr <= addr_cnt3;
                       out_sram0_lb4_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram0_lb4_addr <= addr_cnt4;
                       end
               4'b001x:begin
                       out_sram0_lb1_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram0_lb1_addr <= addr_cnt4;
                       out_sram0_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram0_lb2_addr <= addr_cnt3;
                       out_sram0_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram0_lb3_addr <= addr_cnt2;
                       out_sram0_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram0_lb4_addr <= addr_cnt1;
                       end
               4'bx10x:begin
                       out_sram0_lb1_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram0_lb1_addr <= addr_cnt3;
                       out_sram0_lb2_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram0_lb2_addr <= addr_cnt4;
                       out_sram0_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram0_lb3_addr <= addr_cnt1;
                       out_sram0_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram0_lb4_addr <= addr_cnt2;
                       end
               4'b011x:begin
                       out_sram0_lb1_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram0_lb1_addr <= addr_cnt2;
                       out_sram0_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram0_lb2_addr <= addr_cnt1;
                       out_sram0_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram0_lb3_addr <= addr_cnt4;
                       out_sram0_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram0_lb4_addr <= addr_cnt3;
                       end
                       
               //1026ch case
               //(4'b1000: sram1_din <= nml_r/g/b1  //1st tatal change, (=010x), mix
                         //sram2_din <= nml_r/g/b2
                         //sram3_din <= nml_r/g/b3
                         //sram4_din <= nml_r/g/b4 )

               4'b1011:begin
                       out_sram0_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   //1st half change
                       out_sram0_lb1_addr <= addr_cnt1;
                       out_sram0_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram0_lb2_addr <= addr_cnt2;
                       out_sram0_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram0_lb3_addr <= addr_cnt4;
                       out_sram0_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram0_lb4_addr <= addr_cnt3;
                       end
               4'b1010:begin
                       out_sram0_lb1_wdata <= {r2_d1,g2_d1,b2_d1};  //2nd tatal change, can't mix
                       out_sram0_lb1_addr <= addr_cnt2;
                       out_sram0_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram0_lb2_addr <= addr_cnt1;
                       out_sram0_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram0_lb3_addr <= addr_cnt4;
                       out_sram0_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram0_lb4_addr <= addr_cnt3;
                       end                                        

               //(4'b1100: sram1_din <= nml_r/g/b3  //3rd tatal change, (=010x), mix
                         //sram2_din <= nml_r/g/b4
                         //sram3_din <= nml_r/g/b1
                         //sram4_din <= nml_r/g/b2 )

               4'b1111:begin
                       out_sram0_lb1_wdata <= {r4_d1,g4_d1,b4_d1};   //2nd half change
                       out_sram0_lb1_addr <= addr_cnt4;
                       out_sram0_lb2_wdata <= {r3_d1,g4_d1,b4_d1};
                       out_sram0_lb2_addr <= addr_cnt3;
                       out_sram0_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram0_lb3_addr <= addr_cnt1;
                       out_sram0_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram0_lb4_addr <= addr_cnt2;
                       end                
               4'b1110:begin
                      out_sram0_lb1_wdata <= {r4_d1,g4_d1,b4_d1};   //4th tatal change, can't mix
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb3_addr <= addr_cnt2;
                      out_sram0_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb4_addr <= addr_cnt1;
                      end 
                      endcase        
              end


       3'b100:begin                                                //Dummy head=4,8,12     
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram0_lb1_wdata <= {r1_d2,g1_d2,b1_d2};   
                      out_sram0_lb1_addr <= addr_cnt1;
                      out_sram0_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb2_addr <= addr_cnt2;
                      out_sram0_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb3_addr <= addr_cnt3;
                      out_sram0_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb4_addr <= addr_cnt4;
                      end                                            
               4'b001x:begin
                      out_sram0_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb3_addr <= addr_cnt2;
                      out_sram0_lb4_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram0_lb4_addr <= addr_cnt1;
                      end      
               4'bx10x:begin
                      out_sram0_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram0_lb1_addr <= addr_cnt3;
                      out_sram0_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb2_addr <= addr_cnt4;
                      out_sram0_lb3_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram0_lb3_addr <= addr_cnt1;
                      out_sram0_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb4_addr <= addr_cnt2;
                      end             
              4'b011x:begin
                      out_sram0_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   
                      out_sram0_lb1_addr <= addr_cnt2;
                      out_sram0_lb2_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram0_lb2_addr <= addr_cnt1;
                      out_sram0_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end          
                      
              //1026ch case
                     //(4'b1000: sram1 <= nml_r/g/b1_d1             //1st tatal change, (=010x), mix
                     //sram2 <= nml_r/g/b2_d1
                     //sram3 <= nml_r/g/b3_d1
                     //sram4 <= nml_r/g/b4_d1 )

               4'b1011:begin
                      out_sram0_lb1_wdata <= {r1_d2,g1_d2,b1_d2};   //1st half change
                      out_sram0_lb1_addr <= addr_cnt1;
                      out_sram0_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb2_addr <= addr_cnt2;
                      out_sram0_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end                            
               4'b1010:begin
                      out_sram0_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   //2nd tatal change, can't mix
                      out_sram0_lb1_addr <= addr_cnt2;
                      out_sram0_lb2_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram0_lb2_addr <= addr_cnt1;
                      out_sram0_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end           

              //(4'b1100: sram1_din <= nml_r/g/b3_d1  //3rd tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b4_d1
                     //sram3_din <= nml_r/g/b1_d1
                     //sram4_din <= nml_r/g/b2_d1 )

               4'b1111:begin
                      out_sram0_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //2nd half change
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram0_lb3_addr <= addr_cnt1;
                      out_sram0_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb4_addr <= addr_cnt2;
                      end         
               4'b1110:begin
                      out_sram0_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //4th tatal change, can't mix
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb3_addr <= addr_cnt2;
                      out_sram0_lb4_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram0_lb4_addr <= addr_cnt1;
                      end
                      endcase        
              end
                
       3'bx01:begin                                               //Dummy head=1,5,9,13   
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram0_lb1_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb1_addr <= addr_cnt1;
                      out_sram0_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb2_addr <= addr_cnt2;
                      out_sram0_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb3_addr <= addr_cnt3;
                      out_sram0_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram0_lb4_addr <= addr_cnt4;
                      end              

               4'b001x:begin
                      out_sram0_lb1_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb3_addr <= addr_cnt2;
                      out_sram0_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram0_lb1_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb1_addr <= addr_cnt3;
                      out_sram0_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram0_lb2_addr <= addr_cnt4;
                      out_sram0_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb3_addr <= addr_cnt1;
                      out_sram0_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb4_addr <= addr_cnt2;
                      end
        
               4'b011x:begin
                      out_sram0_lb1_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb1_addr <= addr_cnt2;
                      out_sram0_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb2_addr <= addr_cnt1;
                      out_sram0_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end
                                         
                //1026ch case
                     //(4'b1000: sram1_din <= nml_r/g/b4_d1  //1st tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b1
                     //sram3_din <= nml_r/g/b2
                     //sram4_din <= nml_r/g/b3 )

               4'b1011:begin
                      out_sram0_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //1st half change
                      out_sram0_lb1_addr <= addr_cnt1;
                      out_sram0_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb2_addr <= addr_cnt2;
                      out_sram0_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end                                       

               4'b1010:begin
                      out_sram0_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   //2nd tatal change, can't mix
                      out_sram0_lb1_addr <= addr_cnt2;
                      out_sram0_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb2_addr <= addr_cnt1;
                      out_sram0_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end               
                
               //(4'b1100: sram1_din <= nml_r/g/b2  //3rd tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b3
                     //sram3_din <= nml_r/g/b4_d1
                     //sram4_din <= nml_r/g/b1 )

               4'b1111:begin
                      out_sram0_lb1_wdata <= {r3_d1,g3_d1,b3_d1};   //2nd half change
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb3_addr <= addr_cnt1;
                      out_sram0_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb4_addr <= addr_cnt2;
                      end
                                        
               4'b1110:begin
                      out_sram0_lb1_wdata <= {r3_d1,g3_d1,b3_d1};   //4th tatal change, can't mix
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb3_addr <= addr_cnt2;
                      out_sram0_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb4_addr <= addr_cnt1;
                      end
                      endcase                 
              end
                          
       3'bx10:begin                           //Dummy head=2,6,10,14  
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram0_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram0_lb1_addr <= addr_cnt1;
                      out_sram0_lb2_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram0_lb2_addr <= addr_cnt2;
                      out_sram0_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb3_addr <= addr_cnt3;
                      out_sram0_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb4_addr <= addr_cnt4;
                      end
                        
               4'b001x:begin
                      out_sram0_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram0_lb3_addr <= addr_cnt2;
                      out_sram0_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram0_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   
                      out_sram0_lb1_addr <= addr_cnt3;
                      out_sram0_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb2_addr <= addr_cnt4;
                      out_sram0_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb3_addr <= addr_cnt1;
                      out_sram0_lb4_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram0_lb4_addr <= addr_cnt2;
                      end               

               4'b011x:begin
                      out_sram0_lb1_wdata <= {r4_d2,g4_d2,b1_d2};   
                      out_sram0_lb1_addr <= addr_cnt2;
                      out_sram0_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb2_addr <= addr_cnt1;
                      out_sram0_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end                                       

               //1026ch case

                //(4'b1000: sram1_din <= nml_r/g/b3_d1  //1st tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b4_d1
                      //sram3_din <= nml_r/g/b1
                      //sram4_din <= nml_r/g/b2 )

               4'b1011:begin
                      out_sram0_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   //1st half change
                      out_sram0_lb1_addr <= addr_cnt1;
                      out_sram0_lb2_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram0_lb2_addr <= addr_cnt2;
                      out_sram0_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end

               4'b1010:begin
                      out_sram0_lb1_wdata <= {r4_d2,g4_d2,b1_d2};   //2nd tatal change, can't mix
                      out_sram0_lb1_addr <= addr_cnt2;
                      out_sram0_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb2_addr <= addr_cnt1;
                      out_sram0_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end
                                          
               //(4'b1100: sram1_din <= nml_r/g/b1  //3rd tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b2
                      //sram3_din <= nml_r/g/b3_d1
                      //sram4_din <= nml_r/g/b4_d1 )

               4'b1111:begin
                      out_sram0_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   //2nd half change
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb3_addr <= addr_cnt1;
                      out_sram0_lb4_wdata <= {r4_d2,g4_d2,b4_d2};                                         
                      out_sram0_lb4_addr <= addr_cnt2;
                      end                               

               4'b1110:begin
                      out_sram0_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   //4th tatal change, can't mix
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram0_lb3_addr <= addr_cnt2;
                      out_sram0_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb4_addr <= addr_cnt1;
                      end
               endcase                                    
               end
 
       3'bx11:begin                                           //Dummy head=3,7,11,15 
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram0_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   
                      out_sram0_lb1_addr <= addr_cnt1;
                      out_sram0_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb2_addr <= addr_cnt2;
                      out_sram0_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb3_addr <= addr_cnt3;
                      out_sram0_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb4_addr <= addr_cnt4;
                      end                         

               4'b001x:begin
                      out_sram0_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb3_addr <= addr_cnt2;
                      out_sram0_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram0_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   
                      out_sram0_lb1_addr <= addr_cnt3;
                      out_sram0_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb2_addr <= addr_cnt4;
                      out_sram0_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb3_addr <= addr_cnt1;
                      out_sram0_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb4_addr <= addr_cnt2;
                      end                                       

               4'b011x:begin
                      out_sram0_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram0_lb1_addr <= addr_cnt2;
                      out_sram0_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb2_addr <= addr_cnt1;
                      out_sram0_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end       

               //1026ch case
               //(4'b1000: sram1_din <= nml_r/g/b2_d1  //1st tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b3_d1
                      //sram3_din <= nml_r/g/b4_d1
                      //sram4_din <= nml_r/g/b1 )

               4'b1011:begin
                      out_sram0_lb1_wdata <= {r2_d2,g2_d2,b2_d2};    //1st half change
                      out_sram0_lb1_addr <= addr_cnt1;
                      out_sram0_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb2_addr <= addr_cnt2;
                      out_sram0_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end

               4'b1010:begin
                      out_sram0_lb1_wdata <= {r3_d2,g3_d2,b3_d2};    //2nd tatal change, can't mix
                      out_sram0_lb1_addr <= addr_cnt2;
                      out_sram0_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb2_addr <= addr_cnt1;
                      out_sram0_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram0_lb3_addr <= addr_cnt4;
                      out_sram0_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb4_addr <= addr_cnt3;
                      end

               //(4'b1100: sram1_din <= nml_r/g/b4_d1  //3rd tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b1
                      //sram3_din <= nml_r/g/b2_d1
                      //sram4_din <= nml_r/g/b3_d1 )

               4'b1111:begin
                      out_sram0_lb1_wdata <= {r1_d1,g1_d1,b1_d1};    //2nd half change
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb3_addr <= addr_cnt1;
                      out_sram0_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb4_addr <= addr_cnt2;
                      end

               4'b1110:begin
                      out_sram0_lb1_wdata <= {r1_d1,g1_d1,b1_d1};    //4th tatal change, can't mix
                      out_sram0_lb1_addr <= addr_cnt4;
                      out_sram0_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram0_lb2_addr <= addr_cnt3;
                      out_sram0_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram0_lb3_addr <= addr_cnt2;
                      out_sram0_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram0_lb4_addr <= addr_cnt1;
                      end
                      endcase                
               end
               endcase
               end
               else begin
                    out_sram0_lb1_addr <= 11'd0;
                    out_sram0_lb2_addr <= 11'd0;
                    out_sram0_lb3_addr <= 11'd0;
                    out_sram0_lb4_addr <= 11'd0;
                    out_sram0_lb1_wdata <= 30'd0;
                    out_sram0_lb2_wdata <= 30'd0;
                    out_sram0_lb3_wdata <= 30'd0;
                    out_sram0_lb4_wdata <= 30'd0;
                    end
end


//2nd set SRAM
reg [10:0] out_sram1_lb1_addr, out_sram1_lb2_addr, out_sram1_lb3_addr, out_sram1_lb4_addr;
reg [29:0] out_sram1_lb1_wdata, out_sram1_lb2_wdata, out_sram1_lb3_wdata, out_sram1_lb4_wdata;
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  begin
     out_sram1_lb1_addr <= 11'd0;
     out_sram1_lb2_addr <= 11'd0;
     out_sram1_lb3_addr <= 11'd0;
     out_sram1_lb4_addr <= 11'd0;
     out_sram1_lb1_wdata <= 30'd0;
     out_sram1_lb2_wdata <= 30'd0;
     out_sram1_lb3_wdata <= 30'd0;
     out_sram1_lb4_wdata <= 30'd0;
  end else if ( wr_sram1 ) begin
        casex ({dummy_head_or, dummy_num_head[1:0]})               
        3'b000:begin                                               //Dummy head=0     
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                       out_sram1_lb1_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram1_lb1_addr <= addr_cnt1;
                       out_sram1_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram1_lb2_addr <= addr_cnt2;
                       out_sram1_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram1_lb3_addr <= addr_cnt3;
                       out_sram1_lb4_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram1_lb4_addr <= addr_cnt4;
                       end
               4'b001x:begin
                       out_sram1_lb1_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram1_lb1_addr <= addr_cnt4;
                       out_sram1_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram1_lb2_addr <= addr_cnt3;
                       out_sram1_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram1_lb3_addr <= addr_cnt2;
                       out_sram1_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram1_lb4_addr <= addr_cnt1;
                       end
               4'bx10x:begin
                       out_sram1_lb1_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram1_lb1_addr <= addr_cnt3;
                       out_sram1_lb2_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram1_lb2_addr <= addr_cnt4;
                       out_sram1_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram1_lb3_addr <= addr_cnt1;
                       out_sram1_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram1_lb4_addr <= addr_cnt2;
                       end
               4'b011x:begin
                       out_sram1_lb1_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram1_lb1_addr <= addr_cnt2;
                       out_sram1_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram1_lb2_addr <= addr_cnt1;
                       out_sram1_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram1_lb3_addr <= addr_cnt4;
                       out_sram1_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram1_lb4_addr <= addr_cnt3;
                       end
               //1026ch case
               //(4'b1000: sram1_din <= nml_r/g/b1  //1st tatal change, (=010x), mix
                         //sram2_din <= nml_r/g/b2
                         //sram3_din <= nml_r/g/b3
                         //sram4_din <= nml_r/g/b4 )

               4'b1011:begin
                       out_sram1_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   //1st half change
                       out_sram1_lb1_addr <= addr_cnt1;
                       out_sram1_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram1_lb2_addr <= addr_cnt2;
                       out_sram1_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram1_lb3_addr <= addr_cnt4;
                       out_sram1_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram1_lb4_addr <= addr_cnt3;
                       end

               4'b1010:begin
                       out_sram1_lb1_wdata <= {r2_d1,g2_d1,b2_d1};  //2nd tatal change, can't mix
                       out_sram1_lb1_addr <= addr_cnt2;
                       out_sram1_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram1_lb2_addr <= addr_cnt1;
                       out_sram1_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram1_lb3_addr <= addr_cnt4;
                       out_sram1_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram1_lb4_addr <= addr_cnt3;
                       end
                                           

               //(4'b1100: sram1_din <= nml_r/g/b3  //3rd tatal change, (=010x), mix
                         //sram2_din <= nml_r/g/b4
                         //sram3_din <= nml_r/g/b1
                         //sram4_din <= nml_r/g/b2 )

               4'b1111:begin
                       out_sram1_lb1_wdata <= {r4_d1,g4_d1,b4_d1};   //2nd half change
                       out_sram1_lb1_addr <= addr_cnt4;
                       out_sram1_lb2_wdata <= {r3_d1,g4_d1,b4_d1};
                       out_sram1_lb2_addr <= addr_cnt3;
                       out_sram1_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram1_lb3_addr <= addr_cnt1;
                       out_sram1_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram1_lb4_addr <= addr_cnt2;
                       end
                
               4'b1110:begin
                      out_sram1_lb1_wdata <= {r4_d1,g4_d1,b4_d1};   //4th tatal change, can't mix
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb3_addr <= addr_cnt2;
                      out_sram1_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb4_addr <= addr_cnt1;
                      end 
                      endcase        
                   end


       3'b100:begin                                                //Dummy head=4,8,12     
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram1_lb1_wdata <= {r1_d2,g1_d2,b1_d2};   
                      out_sram1_lb1_addr <= addr_cnt1;
                      out_sram1_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb2_addr <= addr_cnt2;
                      out_sram1_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb3_addr <= addr_cnt3;
                      out_sram1_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb4_addr <= addr_cnt4;
                      end  
                                          
               4'b001x:begin
                      out_sram1_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb3_addr <= addr_cnt2;
                      out_sram1_lb4_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram1_lb4_addr <= addr_cnt1;
                      end                                     

               4'bx10x:begin
                      out_sram1_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram1_lb1_addr <= addr_cnt3;
                      out_sram1_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb2_addr <= addr_cnt4;
                      out_sram1_lb3_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram1_lb3_addr <= addr_cnt1;
                      out_sram1_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb4_addr <= addr_cnt2;
                      end                                     

               4'b011x:begin
                      out_sram1_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   
                      out_sram1_lb1_addr <= addr_cnt2;
                      out_sram1_lb2_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram1_lb2_addr <= addr_cnt1;
                      out_sram1_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end                            

              //1026ch case
                     //(4'b1000: sram1 <= nml_r/g/b1_d1             //1st tatal change, (=010x), mix
                     //sram2 <= nml_r/g/b2_d1
                     //sram3 <= nml_r/g/b3_d1
                     //sram4 <= nml_r/g/b4_d1 )

               4'b1011:begin
                      out_sram1_lb1_wdata <= {r1_d2,g1_d2,b1_d2};   //1st half change
                      out_sram1_lb1_addr <= addr_cnt1;
                      out_sram1_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb2_addr <= addr_cnt2;
                      out_sram1_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end                           

               4'b1010:begin
                      out_sram1_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   //2nd tatal change, can't mix
                      out_sram1_lb1_addr <= addr_cnt2;
                      out_sram1_lb2_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram1_lb2_addr <= addr_cnt1;
                      out_sram1_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end           

              //(4'b1100: sram1_din <= nml_r/g/b3_d1  //3rd tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b4_d1
                     //sram3_din <= nml_r/g/b1_d1
                     //sram4_din <= nml_r/g/b2_d1 )

               4'b1111:begin
                      out_sram1_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //2nd half change
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram1_lb3_addr <= addr_cnt1;
                      out_sram1_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb4_addr <= addr_cnt2;
                      end
                                         
               4'b1110:begin
                      out_sram1_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //4th tatal change, can't mix
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb3_addr <= addr_cnt2;
                      out_sram1_lb4_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram1_lb4_addr <= addr_cnt1;
                      end
              endcase        
              end
                
       3'bx01:begin                                               //Dummy head=1,5,9,13   
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram1_lb1_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb1_addr <= addr_cnt1;
                      out_sram1_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb2_addr <= addr_cnt2;
                      out_sram1_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb3_addr <= addr_cnt3;
                      out_sram1_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram1_lb4_addr <= addr_cnt4;
                      end               

               4'b001x:begin
                      out_sram1_lb1_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb3_addr <= addr_cnt2;
                      out_sram1_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram1_lb1_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb1_addr <= addr_cnt3;
                      out_sram1_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram1_lb2_addr <= addr_cnt4;
                      out_sram1_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb3_addr <= addr_cnt1;
                      out_sram1_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb4_addr <= addr_cnt2;
                      end
        
               4'b011x:begin
                      out_sram1_lb1_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb1_addr <= addr_cnt2;
                      out_sram1_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb2_addr <= addr_cnt1;
                      out_sram1_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end
                                         
                //1026ch case
                     //(4'b1000: sram1_din <= nml_r/g/b4_d1  //1st tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b1
                     //sram3_din <= nml_r/g/b2
                     //sram4_din <= nml_r/g/b3 )

               4'b1011:begin
                      out_sram1_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //1st half change
                      out_sram1_lb1_addr <= addr_cnt1;
                      out_sram1_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb2_addr <= addr_cnt2;
                      out_sram1_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end                                       

               4'b1010:begin
                      out_sram1_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   //2nd tatal change, can't mix
                      out_sram1_lb1_addr <= addr_cnt2;
                      out_sram1_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb2_addr <= addr_cnt1;
                      out_sram1_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end               
                
               //(4'b1100: sram1_din <= nml_r/g/b2  //3rd tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b3
                     //sram3_din <= nml_r/g/b4_d1
                     //sram4_din <= nml_r/g/b1 )

               4'b1111:begin
                      out_sram1_lb1_wdata <= {r3_d1,g3_d1,b3_d1};   //2nd half change
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb3_addr <= addr_cnt1;
                      out_sram1_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb4_addr <= addr_cnt2;
                      end
                                        
               4'b1110:begin
                      out_sram1_lb1_wdata <= {r3_d1,g3_d1,b3_d1};   //4th tatal change, can't mix
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb3_addr <= addr_cnt2;
                      out_sram1_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb4_addr <= addr_cnt1;
                      end
                          endcase                 
                          end
                          
       3'bx10:begin                           //Dummy head=2,6,10,14  
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram1_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram1_lb1_addr <= addr_cnt1;
                      out_sram1_lb2_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram1_lb2_addr <= addr_cnt2;
                      out_sram1_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb3_addr <= addr_cnt3;
                      out_sram1_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb4_addr <= addr_cnt4;
                      end
                        
               4'b001x:begin
                      out_sram1_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram1_lb3_addr <= addr_cnt2;
                      out_sram1_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram1_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   
                      out_sram1_lb1_addr <= addr_cnt3;
                      out_sram1_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb2_addr <= addr_cnt4;
                      out_sram1_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb3_addr <= addr_cnt1;
                      out_sram1_lb4_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram1_lb4_addr <= addr_cnt2;
                      end               

               4'b011x:begin
                      out_sram1_lb1_wdata <= {r4_d2,g4_d2,b1_d2};   
                      out_sram1_lb1_addr <= addr_cnt2;
                      out_sram1_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb2_addr <= addr_cnt1;
                      out_sram1_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end                                       

               //1026ch case

                //(4'b1000: sram1_din <= nml_r/g/b3_d1  //1st tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b4_d1
                      //sram3_din <= nml_r/g/b1
                      //sram4_din <= nml_r/g/b2 )

               4'b1011:begin
                      out_sram1_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   //1st half change
                      out_sram1_lb1_addr <= addr_cnt1;
                      out_sram1_lb2_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram1_lb2_addr <= addr_cnt2;
                      out_sram1_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end

               4'b1010:begin
                      out_sram1_lb1_wdata <= {r4_d2,g4_d2,b1_d2};   //2nd tatal change, can't mix
                      out_sram1_lb1_addr <= addr_cnt2;
                      out_sram1_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb2_addr <= addr_cnt1;
                      out_sram1_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end
                                          
               //(4'b1100: sram1_din <= nml_r/g/b1  //3rd tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b2
                      //sram3_din <= nml_r/g/b3_d1
                      //sram4_din <= nml_r/g/b4_d1 )

               4'b1111:begin
                      out_sram1_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   //2nd half change
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb3_addr <= addr_cnt1;
                      out_sram1_lb4_wdata <= {r4_d2,g4_d2,b4_d2};                                         
                      out_sram1_lb4_addr <= addr_cnt2;
                      end                               

               4'b1110:begin
                      out_sram1_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   //4th tatal change, can't mix
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram1_lb3_addr <= addr_cnt2;
                      out_sram1_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb4_addr <= addr_cnt1;
                      end
               endcase                                    
               end
 
       3'bx11:begin                                           //Dummy head=3,7,11,15 
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram1_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   
                      out_sram1_lb1_addr <= addr_cnt1;
                      out_sram1_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb2_addr <= addr_cnt2;
                      out_sram1_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb3_addr <= addr_cnt3;
                      out_sram1_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb4_addr <= addr_cnt4;
                      end                         

               4'b001x:begin
                      out_sram1_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb3_addr <= addr_cnt2;
                      out_sram1_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram1_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   
                      out_sram1_lb1_addr <= addr_cnt3;
                      out_sram1_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb2_addr <= addr_cnt4;
                      out_sram1_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb3_addr <= addr_cnt1;
                      out_sram1_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb4_addr <= addr_cnt2;
                      end                                       

               4'b011x:begin
                      out_sram1_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram1_lb1_addr <= addr_cnt2;
                      out_sram1_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb2_addr <= addr_cnt1;
                      out_sram1_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end       

               //1026ch case

               //(4'b1000: sram1_din <= nml_r/g/b2_d1  //1st tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b3_d1
                      //sram3_din <= nml_r/g/b4_d1
                      //sram4_din <= nml_r/g/b1 )

               4'b1011:begin
                      out_sram1_lb1_wdata <= {r2_d2,g2_d2,b2_d2};    //1st half change
                      out_sram1_lb1_addr <= addr_cnt1;
                      out_sram1_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb2_addr <= addr_cnt2;
                      out_sram1_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end

               4'b1010:begin
                      out_sram1_lb1_wdata <= {r3_d2,g3_d2,b3_d2};    //2nd tatal change, can't mix
                      out_sram1_lb1_addr <= addr_cnt2;
                      out_sram1_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb2_addr <= addr_cnt1;
                      out_sram1_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram1_lb3_addr <= addr_cnt4;
                      out_sram1_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb4_addr <= addr_cnt3;
                      end

               //(4'b1100: sram1_din <= nml_r/g/b4_d1  //3rd tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b1
                      //sram3_din <= nml_r/g/b2_d1
                      //sram4_din <= nml_r/g/b3_d1 )

               4'b1111:begin
                      out_sram1_lb1_wdata <= {r1_d1,g1_d1,b1_d1};    //2nd half change
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb3_addr <= addr_cnt1;
                      out_sram1_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb4_addr <= addr_cnt2;
                      end

               4'b1110:begin
                      out_sram1_lb1_wdata <= {r1_d1,g1_d1,b1_d1};    //4th tatal change, can't mix
                      out_sram1_lb1_addr <= addr_cnt4;
                      out_sram1_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram1_lb2_addr <= addr_cnt3;
                      out_sram1_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram1_lb3_addr <= addr_cnt2;
                      out_sram1_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram1_lb4_addr <= addr_cnt1;
                      end
                endcase                
               end
        endcase
                end
               else begin
                    out_sram1_lb1_addr <= 11'd0;
                    out_sram1_lb2_addr <= 11'd0;
                    out_sram1_lb3_addr <= 11'd0;
                    out_sram1_lb4_addr <= 11'd0;
                    out_sram1_lb1_wdata <= 30'd0;
                    out_sram1_lb2_wdata <= 30'd0;
                    out_sram1_lb3_wdata <= 30'd0;
                    out_sram1_lb4_wdata <= 30'd0;
                    end
end




//3rd set SRAM
reg [10:0] out_sram2_lb1_addr, out_sram2_lb2_addr, out_sram2_lb3_addr, out_sram2_lb4_addr;
reg [29:0] out_sram2_lb1_wdata, out_sram2_lb2_wdata, out_sram2_lb3_wdata, out_sram2_lb4_wdata;
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  begin
     out_sram2_lb1_addr <= 11'd0;
         out_sram2_lb2_addr <= 11'd0;
         out_sram2_lb3_addr <= 11'd0;
         out_sram2_lb4_addr <= 11'd0;
         out_sram2_lb1_wdata <= 30'd0;
         out_sram2_lb2_wdata <= 30'd0;
         out_sram2_lb3_wdata <= 30'd0;
         out_sram2_lb4_wdata <= 30'd0;
  end else if ( wr_sram2 ) begin
            casex ({dummy_head_or, dummy_num_head[1:0]})               
        3'b000:begin                                               //Dummy head=0     
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                       out_sram2_lb1_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram2_lb1_addr <= addr_cnt1;
                       out_sram2_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram2_lb2_addr <= addr_cnt2;
                       out_sram2_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram2_lb3_addr <= addr_cnt3;
                       out_sram2_lb4_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram2_lb4_addr <= addr_cnt4;
                       end
               4'b001x:begin
                       out_sram2_lb1_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram2_lb1_addr <= addr_cnt4;
                       out_sram2_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram2_lb2_addr <= addr_cnt3;
                       out_sram2_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram2_lb3_addr <= addr_cnt2;
                       out_sram2_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram2_lb4_addr <= addr_cnt1;
                       end
               4'bx10x:begin
                       out_sram2_lb1_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram2_lb1_addr <= addr_cnt3;
                       out_sram2_lb2_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram2_lb2_addr <= addr_cnt4;
                       out_sram2_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram2_lb3_addr <= addr_cnt1;
                       out_sram2_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram2_lb4_addr <= addr_cnt2;
                       end
               4'b011x:begin
                       out_sram2_lb1_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram2_lb1_addr <= addr_cnt2;
                       out_sram2_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram2_lb2_addr <= addr_cnt1;
                       out_sram2_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram2_lb3_addr <= addr_cnt4;
                       out_sram2_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram2_lb4_addr <= addr_cnt3;
                       end
               //1026ch case
               //(4'b1000: sram1_din <= nml_r/g/b1  //1st tatal change, (=010x), mix
                         //sram2_din <= nml_r/g/b2
                         //sram3_din <= nml_r/g/b3
                         //sram4_din <= nml_r/g/b4 )

               4'b1011:begin
                       out_sram2_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   //1st half change
                       out_sram2_lb1_addr <= addr_cnt1;
                       out_sram2_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram2_lb2_addr <= addr_cnt2;
                       out_sram2_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram2_lb3_addr <= addr_cnt4;
                       out_sram2_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram2_lb4_addr <= addr_cnt3;
                       end

               4'b1010:begin
                       out_sram2_lb1_wdata <= {r2_d1,g2_d1,b2_d1};  //2nd tatal change, can't mix
                       out_sram2_lb1_addr <= addr_cnt2;
                       out_sram2_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram2_lb2_addr <= addr_cnt1;
                       out_sram2_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram2_lb3_addr <= addr_cnt4;
                       out_sram2_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram2_lb4_addr <= addr_cnt3;
                       end                                           

               //(4'b1100: sram1_din <= nml_r/g/b3  //3rd tatal change, (=010x), mix
                         //sram2_din <= nml_r/g/b4
                         //sram3_din <= nml_r/g/b1
                         //sram4_din <= nml_r/g/b2 )

               4'b1111:begin
                       out_sram2_lb1_wdata <= {r4_d1,g4_d1,b4_d1};   //2nd half change
                       out_sram2_lb1_addr <= addr_cnt4;
                       out_sram2_lb2_wdata <= {r3_d1,g4_d1,b4_d1};
                       out_sram2_lb2_addr <= addr_cnt3;
                       out_sram2_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram2_lb3_addr <= addr_cnt1;
                       out_sram2_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram2_lb4_addr <= addr_cnt2;
                       end
                
               4'b1110:begin
                      out_sram2_lb1_wdata <= {r4_d1,g4_d1,b4_d1};   //4th tatal change, can't mix
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb3_addr <= addr_cnt2;
                      out_sram2_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb4_addr <= addr_cnt1;
                      end 
                   endcase        
                   end


       3'b100:begin                                                //Dummy head=4,8,12     
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram2_lb1_wdata <= {r1_d2,g1_d2,b1_d2};   
                      out_sram2_lb1_addr <= addr_cnt1;
                      out_sram2_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb2_addr <= addr_cnt2;
                      out_sram2_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb3_addr <= addr_cnt3;
                      out_sram2_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb4_addr <= addr_cnt4;
                                          end  
                                          
               4'b001x:begin
                      out_sram2_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb3_addr <= addr_cnt2;
                      out_sram2_lb4_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram2_lb4_addr <= addr_cnt1;
                      end                                     

               4'bx10x:begin
                      out_sram2_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram2_lb1_addr <= addr_cnt3;
                      out_sram2_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb2_addr <= addr_cnt4;
                      out_sram2_lb3_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram2_lb3_addr <= addr_cnt1;
                      out_sram2_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb4_addr <= addr_cnt2;
                                          end                                     

               4'b011x:begin
                      out_sram2_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   
                      out_sram2_lb1_addr <= addr_cnt2;
                      out_sram2_lb2_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram2_lb2_addr <= addr_cnt1;
                      out_sram2_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end                                 

              //1026ch case
                     //(4'b1000: sram1 <= nml_r/g/b1_d1             //1st tatal change, (=010x), mix
                     //sram2 <= nml_r/g/b2_d1
                     //sram3 <= nml_r/g/b3_d1
                     //sram4 <= nml_r/g/b4_d1 )

               4'b1011:begin
                      out_sram2_lb1_wdata <= {r1_d2,g1_d2,b1_d2};   //1st half change
                      out_sram2_lb1_addr <= addr_cnt1;
                      out_sram2_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb2_addr <= addr_cnt2;
                      out_sram2_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end                   

               4'b1010:begin
                      out_sram2_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   //2nd tatal change, can't mix
                      out_sram2_lb1_addr <= addr_cnt2;
                      out_sram2_lb2_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram2_lb2_addr <= addr_cnt1;
                      out_sram2_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end           

              //(4'b1100: sram1_din <= nml_r/g/b3_d1  //3rd tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b4_d1
                     //sram3_din <= nml_r/g/b1_d1
                     //sram4_din <= nml_r/g/b2_d1 )

               4'b1111:begin
                      out_sram2_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //2nd half change
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram2_lb3_addr <= addr_cnt1;
                      out_sram2_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb4_addr <= addr_cnt2;
                      end
                                         
               4'b1110:begin
                      out_sram2_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //4th tatal change, can't mix
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb3_addr <= addr_cnt2;
                      out_sram2_lb4_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram2_lb4_addr <= addr_cnt1;
                      end
               endcase        
               end
                
       3'bx01:begin                                               //Dummy head=1,5,9,13   
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram2_lb1_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb1_addr <= addr_cnt1;
                      out_sram2_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb2_addr <= addr_cnt2;
                      out_sram2_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb3_addr <= addr_cnt3;
                      out_sram2_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram2_lb4_addr <= addr_cnt4;
                      end               

               4'b001x:begin
                      out_sram2_lb1_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb3_addr <= addr_cnt2;
                      out_sram2_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram2_lb1_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb1_addr <= addr_cnt3;
                      out_sram2_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram2_lb2_addr <= addr_cnt4;
                      out_sram2_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb3_addr <= addr_cnt1;
                      out_sram2_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb4_addr <= addr_cnt2;
                      end
        
               4'b011x:begin
                      out_sram2_lb1_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb1_addr <= addr_cnt2;
                      out_sram2_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb2_addr <= addr_cnt1;
                      out_sram2_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end
                                         
                //1026ch case
                     //(4'b1000: sram1_din <= nml_r/g/b4_d1  //1st tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b1
                     //sram3_din <= nml_r/g/b2
                     //sram4_din <= nml_r/g/b3 )

               4'b1011:begin
                      out_sram2_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //1st half change
                      out_sram2_lb1_addr <= addr_cnt1;
                      out_sram2_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb2_addr <= addr_cnt2;
                      out_sram2_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end                                       

               4'b1010:begin
                      out_sram2_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   //2nd tatal change, can't mix
                      out_sram2_lb1_addr <= addr_cnt2;
                      out_sram2_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb2_addr <= addr_cnt1;
                      out_sram2_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end               
                
               //(4'b1100: sram1_din <= nml_r/g/b2  //3rd tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b3
                     //sram3_din <= nml_r/g/b4_d1
                     //sram4_din <= nml_r/g/b1 )

               4'b1111:begin
                      out_sram2_lb1_wdata <= {r3_d1,g3_d1,b3_d1};   //2nd half change
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb3_addr <= addr_cnt1;
                      out_sram2_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb4_addr <= addr_cnt2;
                      end
                                        
               4'b1110:begin
                      out_sram2_lb1_wdata <= {r3_d1,g3_d1,b3_d1};   //4th tatal change, can't mix
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb3_addr <= addr_cnt2;
                      out_sram2_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb4_addr <= addr_cnt1;
                      end
                 endcase                 
                 end
                          
       3'bx10:begin                           //Dummy head=2,6,10,14  
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram2_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram2_lb1_addr <= addr_cnt1;
                      out_sram2_lb2_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram2_lb2_addr <= addr_cnt2;
                      out_sram2_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb3_addr <= addr_cnt3;
                      out_sram2_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb4_addr <= addr_cnt4;
                      end
                        
               4'b001x:begin
                      out_sram2_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram2_lb3_addr <= addr_cnt2;
                      out_sram2_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram2_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   
                      out_sram2_lb1_addr <= addr_cnt3;
                      out_sram2_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb2_addr <= addr_cnt4;
                      out_sram2_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb3_addr <= addr_cnt1;
                      out_sram2_lb4_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram2_lb4_addr <= addr_cnt2;
                      end               

               4'b011x:begin
                      out_sram2_lb1_wdata <= {r4_d2,g4_d2,b1_d2};   
                      out_sram2_lb1_addr <= addr_cnt2;
                      out_sram2_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb2_addr <= addr_cnt1;
                      out_sram2_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end                                       

               //1026ch case
                //(4'b1000: sram1_din <= nml_r/g/b3_d1  //1st tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b4_d1
                      //sram3_din <= nml_r/g/b1
                      //sram4_din <= nml_r/g/b2 )

               4'b1011:begin
                      out_sram2_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   //1st half change
                      out_sram2_lb1_addr <= addr_cnt1;
                      out_sram2_lb2_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram2_lb2_addr <= addr_cnt2;
                      out_sram2_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end

               4'b1010:begin
                      out_sram2_lb1_wdata <= {r4_d2,g4_d2,b1_d2};   //2nd tatal change, can't mix
                      out_sram2_lb1_addr <= addr_cnt2;
                      out_sram2_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb2_addr <= addr_cnt1;
                      out_sram2_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end
                                          
               //(4'b1100: sram1_din <= nml_r/g/b1  //3rd tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b2
                      //sram3_din <= nml_r/g/b3_d1
                      //sram4_din <= nml_r/g/b4_d1 )

               4'b1111:begin
                      out_sram2_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   //2nd half change
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb3_addr <= addr_cnt1;
                      out_sram2_lb4_wdata <= {r4_d2,g4_d2,b4_d2};                                         
                      out_sram2_lb4_addr <= addr_cnt2;
                      end                               

               4'b1110:begin
                      out_sram2_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   //4th tatal change, can't mix
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram2_lb3_addr <= addr_cnt2;
                      out_sram2_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb4_addr <= addr_cnt1;
                      end
               endcase                                    
                       end
 
       3'bx11:begin                                           //Dummy head=3,7,11,15 
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram2_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   
                      out_sram2_lb1_addr <= addr_cnt1;
                      out_sram2_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb2_addr <= addr_cnt2;
                      out_sram2_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb3_addr <= addr_cnt3;
                      out_sram2_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb4_addr <= addr_cnt4;
                      end                         

               4'b001x:begin
                      out_sram2_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb3_addr <= addr_cnt2;
                      out_sram2_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram2_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   
                      out_sram2_lb1_addr <= addr_cnt3;
                      out_sram2_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb2_addr <= addr_cnt4;
                      out_sram2_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb3_addr <= addr_cnt1;
                      out_sram2_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb4_addr <= addr_cnt2;
                      end                                       

               4'b011x:begin
                      out_sram2_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram2_lb1_addr <= addr_cnt2;
                      out_sram2_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb2_addr <= addr_cnt1;
                      out_sram2_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end       

               //1026ch case

               //(4'b1000: sram1_din <= nml_r/g/b2_d1  //1st tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b3_d1
                      //sram3_din <= nml_r/g/b4_d1
                      //sram4_din <= nml_r/g/b1 )

               4'b1011:begin
                      out_sram2_lb1_wdata <= {r2_d2,g2_d2,b2_d2};    //1st half change
                      out_sram2_lb1_addr <= addr_cnt1;
                      out_sram2_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb2_addr <= addr_cnt2;
                      out_sram2_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end

               4'b1010:begin
                      out_sram2_lb1_wdata <= {r3_d2,g3_d2,b3_d2};    //2nd tatal change, can't mix
                      out_sram2_lb1_addr <= addr_cnt2;
                      out_sram2_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb2_addr <= addr_cnt1;
                      out_sram2_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram2_lb3_addr <= addr_cnt4;
                      out_sram2_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb4_addr <= addr_cnt3;
                      end

               //(4'b1100: sram1_din <= nml_r/g/b4_d1  //3rd tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b1
                      //sram3_din <= nml_r/g/b2_d1
                      //sram4_din <= nml_r/g/b3_d1 )

               4'b1111:begin
                      out_sram2_lb1_wdata <= {r1_d1,g1_d1,b1_d1};    //2nd half change
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb3_addr <= addr_cnt1;
                      out_sram2_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb4_addr <= addr_cnt2;
                      end

               4'b1110:begin
                      out_sram2_lb1_wdata <= {r1_d1,g1_d1,b1_d1};    //4th tatal change, can't mix
                      out_sram2_lb1_addr <= addr_cnt4;
                      out_sram2_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram2_lb2_addr <= addr_cnt3;
                      out_sram2_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram2_lb3_addr <= addr_cnt2;
                      out_sram2_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram2_lb4_addr <= addr_cnt1;
                      end
                           endcase                
               end
        endcase
                end
               else begin
                    out_sram2_lb1_addr <= 11'd0;
                    out_sram2_lb2_addr <= 11'd0;
                    out_sram2_lb3_addr <= 11'd0;
                    out_sram2_lb4_addr <= 11'd0;
                    out_sram2_lb1_wdata <= 30'd0;
                    out_sram2_lb2_wdata <= 30'd0;
                    out_sram2_lb3_wdata <= 30'd0;
                    out_sram2_lb4_wdata <= 30'd0;
                                end
end





//4th set SRAM
reg [10:0] out_sram3_lb1_addr, out_sram3_lb2_addr, out_sram3_lb3_addr, out_sram3_lb4_addr;
reg [29:0] out_sram3_lb1_wdata, out_sram3_lb2_wdata, out_sram3_lb3_wdata, out_sram3_lb4_wdata;
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  begin
     out_sram3_lb1_addr <= 11'd0;
         out_sram3_lb2_addr <= 11'd0;
         out_sram3_lb3_addr <= 11'd0;
         out_sram3_lb4_addr <= 11'd0;
         out_sram3_lb1_wdata <= 30'd0;
         out_sram3_lb2_wdata <= 30'd0;
         out_sram3_lb3_wdata <= 30'd0;
         out_sram3_lb4_wdata <= 30'd0;
  end else if ( wr_sram3 ) begin
            casex ({dummy_head_or, dummy_num_head[1:0]})               
        3'b000:begin                                               //Dummy head=0     
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                       out_sram3_lb1_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram3_lb1_addr <= addr_cnt1;
                       out_sram3_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram3_lb2_addr <= addr_cnt2;
                       out_sram3_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram3_lb3_addr <= addr_cnt3;
                       out_sram3_lb4_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram3_lb4_addr <= addr_cnt4;
                       end
               4'b001x:begin
                       out_sram3_lb1_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram3_lb1_addr <= addr_cnt4;
                       out_sram3_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram3_lb2_addr <= addr_cnt3;
                       out_sram3_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram3_lb3_addr <= addr_cnt2;
                       out_sram3_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram3_lb4_addr <= addr_cnt1;
                                           end
               4'bx10x:begin
                       out_sram3_lb1_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram3_lb1_addr <= addr_cnt3;
                       out_sram3_lb2_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram3_lb2_addr <= addr_cnt4;
                       out_sram3_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram3_lb3_addr <= addr_cnt1;
                       out_sram3_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram3_lb4_addr <= addr_cnt2;
                       end
               4'b011x:begin
                       out_sram3_lb1_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram3_lb1_addr <= addr_cnt2;
                       out_sram3_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram3_lb2_addr <= addr_cnt1;
                       out_sram3_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram3_lb3_addr <= addr_cnt4;
                       out_sram3_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram3_lb4_addr <= addr_cnt3;
                       end
               //1026ch case
               //(4'b1000: sram1_din <= nml_r/g/b1  //1st tatal change, (=010x), mix
                         //sram2_din <= nml_r/g/b2
                         //sram3_din <= nml_r/g/b3
                         //sram4_din <= nml_r/g/b4 )

               4'b1011:begin
                       out_sram3_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   //1st half change
                       out_sram3_lb1_addr <= addr_cnt1;
                       out_sram3_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram3_lb2_addr <= addr_cnt2;
                       out_sram3_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram3_lb3_addr <= addr_cnt4;
                       out_sram3_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram3_lb4_addr <= addr_cnt3;
                       end

               4'b1010:begin
                       out_sram3_lb1_wdata <= {r2_d1,g2_d1,b2_d1};  //2nd tatal change, can't mix
                       out_sram3_lb1_addr <= addr_cnt2;
                       out_sram3_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram3_lb2_addr <= addr_cnt1;
                       out_sram3_lb3_wdata <= {r4_d1,g4_d1,b4_d1};
                       out_sram3_lb3_addr <= addr_cnt4;
                       out_sram3_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                       out_sram3_lb4_addr <= addr_cnt3;
                       end                                           

               //(4'b1100: sram1_din <= nml_r/g/b3  //3rd tatal change, (=010x), mix
                         //sram2_din <= nml_r/g/b4
                         //sram3_din <= nml_r/g/b1
                         //sram4_din <= nml_r/g/b2 )

               4'b1111:begin
                       out_sram3_lb1_wdata <= {r4_d1,g4_d1,b4_d1};   //2nd half change
                       out_sram3_lb1_addr <= addr_cnt4;
                       out_sram3_lb2_wdata <= {r3_d1,g4_d1,b4_d1};
                       out_sram3_lb2_addr <= addr_cnt3;
                       out_sram3_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                       out_sram3_lb3_addr <= addr_cnt1;
                       out_sram3_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                       out_sram3_lb4_addr <= addr_cnt2;
                       end
                
               4'b1110:begin
                      out_sram3_lb1_wdata <= {r4_d1,g4_d1,b4_d1};   //4th tatal change, can't mix
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb3_addr <= addr_cnt2;
                      out_sram3_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb4_addr <= addr_cnt1;
                      end 
                 endcase        
                 end

       3'b100:begin                                                //Dummy head=4,8,12     
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram3_lb1_wdata <= {r1_d2,g1_d2,b1_d2};   
                      out_sram3_lb1_addr <= addr_cnt1;
                      out_sram3_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb2_addr <= addr_cnt2;
                      out_sram3_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb3_addr <= addr_cnt3;
                      out_sram3_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb4_addr <= addr_cnt4;
                      end  
                                          
               4'b001x:begin
                      out_sram3_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb3_addr <= addr_cnt2;
                      out_sram3_lb4_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram3_lb4_addr <= addr_cnt1;
                      end                                     

               4'bx10x:begin
                      out_sram3_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram3_lb1_addr <= addr_cnt3;
                      out_sram3_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb2_addr <= addr_cnt4;
                      out_sram3_lb3_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram3_lb3_addr <= addr_cnt1;
                      out_sram3_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb4_addr <= addr_cnt2;
                      end                                     

               4'b011x:begin
                      out_sram3_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   
                      out_sram3_lb1_addr <= addr_cnt2;
                      out_sram3_lb2_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram3_lb2_addr <= addr_cnt1;
                      out_sram3_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end                                

              //1026ch case
                     //(4'b1000: sram1 <= nml_r/g/b1_d1             //1st tatal change, (=010x), mix
                     //sram2 <= nml_r/g/b2_d1
                     //sram3 <= nml_r/g/b3_d1
                     //sram4 <= nml_r/g/b4_d1 )

               4'b1011:begin
                      out_sram3_lb1_wdata <= {r1_d2,g1_d2,b1_d2};   //1st half change
                      out_sram3_lb1_addr <= addr_cnt1;
                      out_sram3_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb2_addr <= addr_cnt2;
                      out_sram3_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end                            

               4'b1010:begin
                      out_sram3_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   //2nd tatal change, can't mix
                      out_sram3_lb1_addr <= addr_cnt2;
                      out_sram3_lb2_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram3_lb2_addr <= addr_cnt1;
                      out_sram3_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end           

              //(4'b1100: sram1_din <= nml_r/g/b3_d1  //3rd tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b4_d1
                     //sram3_din <= nml_r/g/b1_d1
                     //sram4_din <= nml_r/g/b2_d1 )

               4'b1111:begin
                      out_sram3_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //2nd half change
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram3_lb3_addr <= addr_cnt1;
                      out_sram3_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb4_addr <= addr_cnt2;
                      end
                                         
               4'b1110:begin
                      out_sram3_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //4th tatal change, can't mix
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb3_addr <= addr_cnt2;
                      out_sram3_lb4_wdata <= {r1_d2,g1_d2,b1_d2};
                      out_sram3_lb4_addr <= addr_cnt1;
                      end
                endcase        
                end
                
       3'bx01:begin                                               //Dummy head=1,5,9,13   
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram3_lb1_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb1_addr <= addr_cnt1;
                      out_sram3_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb2_addr <= addr_cnt2;
                      out_sram3_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb3_addr <= addr_cnt3;
                      out_sram3_lb4_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram3_lb4_addr <= addr_cnt4;
                      end               

               4'b001x:begin
                      out_sram3_lb1_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb3_addr <= addr_cnt2;
                      out_sram3_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram3_lb1_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb1_addr <= addr_cnt3;
                      out_sram3_lb2_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram3_lb2_addr <= addr_cnt4;
                      out_sram3_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb3_addr <= addr_cnt1;
                      out_sram3_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb4_addr <= addr_cnt2;
                      end
        
               4'b011x:begin
                      out_sram3_lb1_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb1_addr <= addr_cnt2;
                      out_sram3_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb2_addr <= addr_cnt1;
                      out_sram3_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end
                                         
                //1026ch case
                     //(4'b1000: sram1_din <= nml_r/g/b4_d1  //1st tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b1
                     //sram3_din <= nml_r/g/b2
                     //sram4_din <= nml_r/g/b3 )

               4'b1011:begin
                      out_sram3_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   //1st half change
                      out_sram3_lb1_addr <= addr_cnt1;
                      out_sram3_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb2_addr <= addr_cnt2;
                      out_sram3_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end                                       

               4'b1010:begin
                      out_sram3_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   //2nd tatal change, can't mix
                      out_sram3_lb1_addr <= addr_cnt2;
                      out_sram3_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb2_addr <= addr_cnt1;
                      out_sram3_lb3_wdata <= {r3_d1,g3_d1,b3_d1};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end               
                
               //(4'b1100: sram1_din <= nml_r/g/b2  //3rd tatal change, (=010x), mix
                     //sram2_din <= nml_r/g/b3
                     //sram3_din <= nml_r/g/b4_d1
                     //sram4_din <= nml_r/g/b1 )

               4'b1111:begin
                      out_sram3_lb1_wdata <= {r3_d1,g3_d1,b3_d1};   //2nd half change
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb3_addr <= addr_cnt1;
                      out_sram3_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb4_addr <= addr_cnt2;
                      end
                                        
               4'b1110:begin
                      out_sram3_lb1_wdata <= {r3_d1,g3_d1,b3_d1};   //4th tatal change, can't mix
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb3_addr <= addr_cnt2;
                      out_sram3_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb4_addr <= addr_cnt1;
                      end
              endcase                 
              end
                          
       3'bx10:begin                           //Dummy head=2,6,10,14  
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram3_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram3_lb1_addr <= addr_cnt1;
                      out_sram3_lb2_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram3_lb2_addr <= addr_cnt2;
                      out_sram3_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb3_addr <= addr_cnt3;
                      out_sram3_lb4_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb4_addr <= addr_cnt4;
                      end
                        
               4'b001x:begin
                      out_sram3_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram3_lb3_addr <= addr_cnt2;
                      out_sram3_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram3_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   
                      out_sram3_lb1_addr <= addr_cnt3;
                      out_sram3_lb2_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb2_addr <= addr_cnt4;
                      out_sram3_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb3_addr <= addr_cnt1;
                      out_sram3_lb4_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram3_lb4_addr <= addr_cnt2;
                      end               

               4'b011x:begin
                      out_sram3_lb1_wdata <= {r4_d2,g4_d2,b1_d2};   
                      out_sram3_lb1_addr <= addr_cnt2;
                      out_sram3_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb2_addr <= addr_cnt1;
                      out_sram3_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end                                       

               //1026ch case

                //(4'b1000: sram1_din <= nml_r/g/b3_d1  //1st tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b4_d1
                      //sram3_din <= nml_r/g/b1
                      //sram4_din <= nml_r/g/b2 )

               4'b1011:begin
                      out_sram3_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   //1st half change
                      out_sram3_lb1_addr <= addr_cnt1;
                      out_sram3_lb2_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram3_lb2_addr <= addr_cnt2;
                      out_sram3_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end

               4'b1010:begin
                      out_sram3_lb1_wdata <= {r4_d2,g4_d2,b1_d2};   //2nd tatal change, can't mix
                      out_sram3_lb1_addr <= addr_cnt2;
                      out_sram3_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb2_addr <= addr_cnt1;
                      out_sram3_lb3_wdata <= {r2_d1,g2_d1,b2_d1};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end
                                          
               //(4'b1100: sram1_din <= nml_r/g/b1  //3rd tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b2
                      //sram3_din <= nml_r/g/b3_d1
                      //sram4_din <= nml_r/g/b4_d1 )

               4'b1111:begin
                      out_sram3_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   //2nd half change
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb3_addr <= addr_cnt1;
                      out_sram3_lb4_wdata <= {r4_d2,g4_d2,b4_d2};                                         
                      out_sram3_lb4_addr <= addr_cnt2;
                      end                               

               4'b1110:begin
                      out_sram3_lb1_wdata <= {r2_d1,g2_d1,b2_d1};   //4th tatal change, can't mix
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r4_d2,g4_d2,b1_d2};
                      out_sram3_lb3_addr <= addr_cnt2;
                      out_sram3_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb4_addr <= addr_cnt1;
                      end
               endcase                                    
               end
 
       3'bx11:begin                                           //Dummy head=3,7,11,15 
               casex({~sd_div4, lb_change[1:0], addr_mid_stop_d1})
               4'bx00x:begin
                      out_sram3_lb1_wdata <= {r2_d2,g2_d2,b2_d2};   
                      out_sram3_lb1_addr <= addr_cnt1;
                      out_sram3_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb2_addr <= addr_cnt2;
                      out_sram3_lb3_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb3_addr <= addr_cnt3;
                      out_sram3_lb4_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb4_addr <= addr_cnt4;
                      end                         

               4'b001x:begin
                      out_sram3_lb1_wdata <= {r1_d1,g1_d1,b1_d1};   
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb3_addr <= addr_cnt2;
                      out_sram3_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb4_addr <= addr_cnt1;
                      end

               4'bx10x:begin
                      out_sram3_lb1_wdata <= {r4_d2,g4_d2,b4_d2};   
                      out_sram3_lb1_addr <= addr_cnt3;
                      out_sram3_lb2_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb2_addr <= addr_cnt4;
                      out_sram3_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb3_addr <= addr_cnt1;
                      out_sram3_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb4_addr <= addr_cnt2;
                      end                                       

               4'b011x:begin
                      out_sram3_lb1_wdata <= {r3_d2,g3_d2,b3_d2};   
                      out_sram3_lb1_addr <= addr_cnt2;
                      out_sram3_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb2_addr <= addr_cnt1;
                      out_sram3_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end       

               //1026ch case
               //(4'b1000: sram1_din <= nml_r/g/b2_d1  //1st tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b3_d1
                      //sram3_din <= nml_r/g/b4_d1
                      //sram4_din <= nml_r/g/b1 )

               4'b1011:begin
                      out_sram3_lb1_wdata <= {r2_d2,g2_d2,b2_d2};    //1st half change
                      out_sram3_lb1_addr <= addr_cnt1;
                      out_sram3_lb2_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb2_addr <= addr_cnt2;
                      out_sram3_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end

               4'b1010:begin
                      out_sram3_lb1_wdata <= {r3_d2,g3_d2,b3_d2};    //2nd tatal change, can't mix
                      out_sram3_lb1_addr <= addr_cnt2;
                      out_sram3_lb2_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb2_addr <= addr_cnt1;
                      out_sram3_lb3_wdata <= {r1_d1,g1_d1,b1_d1};
                      out_sram3_lb3_addr <= addr_cnt4;
                      out_sram3_lb4_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb4_addr <= addr_cnt3;
                      end

               //(4'b1100: sram1_din <= nml_r/g/b4_d1  //3rd tatal change, (=010x), mix
                      //sram2_din <= nml_r/g/b1
                      //sram3_din <= nml_r/g/b2_d1
                      //sram4_din <= nml_r/g/b3_d1 )

               4'b1111:begin
                      out_sram3_lb1_wdata <= {r1_d1,g1_d1,b1_d1};    //2nd half change
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb3_addr <= addr_cnt1;
                      out_sram3_lb4_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb4_addr <= addr_cnt2;
                      end

               4'b1110:begin
                      out_sram3_lb1_wdata <= {r1_d1,g1_d1,b1_d1};    //4th tatal change, can't mix
                      out_sram3_lb1_addr <= addr_cnt4;
                      out_sram3_lb2_wdata <= {r4_d2,g4_d2,b4_d2};
                      out_sram3_lb2_addr <= addr_cnt3;
                      out_sram3_lb3_wdata <= {r3_d2,g3_d2,b3_d2};
                      out_sram3_lb3_addr <= addr_cnt2;
                      out_sram3_lb4_wdata <= {r2_d2,g2_d2,b2_d2};
                      out_sram3_lb4_addr <= addr_cnt1;
                      end
               endcase                
               end
        endcase
                end
               else begin
                    out_sram3_lb1_addr <= 11'd0;
                    out_sram3_lb2_addr <= 11'd0;
                    out_sram3_lb3_addr <= 11'd0;
                    out_sram3_lb4_addr <= 11'd0;
                    out_sram3_lb1_wdata <= 30'd0;
                    out_sram3_lb2_wdata <= 30'd0;
                    out_sram3_lb3_wdata <= 30'd0;
                    out_sram3_lb4_wdata <= 30'd0;
                                end
end


//read out from sram

reg [10:0] addr_last;
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  addr_last <= 11'd0;
else 
  addr_last <= in_hact + {6'd0, port_num} -11'd1;    
end

reg [10:0] read_out_start; 
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  read_out_start <= 11'd0;
  else if ( data_rvs )
       read_out_start <= addr_last;
           else
           read_out_start <= 11'd0;
end


//1st set SRAM 
wire out_rd_sram0_pe = xdio_d2 & out_rd_sram0;
reg [10:0] r_out_sram0_lb1_addr, r_out_sram0_lb2_addr, r_out_sram0_lb3_addr, r_out_sram0_lb4_addr;   
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  begin
     r_out_sram0_lb1_addr <= 11'd0;
     r_out_sram0_lb2_addr <= 11'd0;
     r_out_sram0_lb3_addr <= 11'd0;
     r_out_sram0_lb4_addr <= 11'd0;    
  end else if ( out_rd_sram0_pe ) begin
           r_out_sram0_lb1_addr <= read_out_start;
           r_out_sram0_lb2_addr <= read_out_start;
           r_out_sram0_lb3_addr <= read_out_start;
           r_out_sram0_lb4_addr <= read_out_start;  end
               else if ( data_rvs & out_rd_sram0) begin          //data_rvs=1, out_rd_sram0=1 
                   r_out_sram0_lb1_addr <= out_sram0_lb1_addr - 11'd1;
                   r_out_sram0_lb2_addr <= out_sram0_lb2_addr - 11'd1;
                   r_out_sram0_lb3_addr <= out_sram0_lb3_addr - 11'd1;
                   r_out_sram0_lb4_addr <= out_sram0_lb4_addr - 11'd1;  end
                        else if ( ~data_rvs & out_rd_sram0) begin    //data_rvs=0, out_rd_sram0=1
                                r_out_sram0_lb1_addr <= out_sram0_lb1_addr + 11'd1;
                                r_out_sram0_lb2_addr <= out_sram0_lb2_addr + 11'd1;
                                r_out_sram0_lb3_addr <= out_sram0_lb3_addr + 11'd1;
                                r_out_sram0_lb4_addr <= out_sram0_lb4_addr + 11'd1;  end
                                     else begin
                                         r_out_sram0_lb1_addr <= 11'd0;
                                         r_out_sram0_lb2_addr <= 11'd0;
                                         r_out_sram0_lb3_addr <= 11'd0;
                                         r_out_sram0_lb4_addr <= 11'd0;  end                                       
end



//2nd set SRAM 
wire out_rd_sram1_pe = xdio_d2 & out_rd_sram1;
reg [10:0] r_out_sram1_lb1_addr, r_out_sram1_lb2_addr, r_out_sram1_lb3_addr, r_out_sram1_lb4_addr;    
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  begin
     r_out_sram1_lb1_addr <= 11'd0;
     r_out_sram1_lb2_addr <= 11'd0;
     r_out_sram1_lb3_addr <= 11'd0;
     r_out_sram1_lb4_addr <= 11'd0;    
  end else if ( out_rd_sram0_pe ) begin
           r_out_sram1_lb1_addr <= read_out_start;
           r_out_sram1_lb2_addr <= read_out_start;
           r_out_sram1_lb3_addr <= read_out_start;
           r_out_sram1_lb4_addr <= read_out_start;  end
               else if ( data_rvs & out_rd_sram0) begin          //data_rvs=1, out_rd_sram0=1 
                    r_out_sram1_lb1_addr <= out_sram1_lb1_addr - 11'd1;
                    r_out_sram1_lb2_addr <= out_sram1_lb2_addr - 11'd1;
                    r_out_sram1_lb3_addr <= out_sram1_lb3_addr - 11'd1;
                    r_out_sram1_lb4_addr <= out_sram1_lb4_addr - 11'd1;  end
                        else if ( ~data_rvs & out_rd_sram0) begin    //data_rvs=0, out_rd_sram0=1
                             r_out_sram1_lb1_addr <= out_sram1_lb1_addr + 11'd1;
                             r_out_sram1_lb2_addr <= out_sram1_lb2_addr + 11'd1;
                             r_out_sram1_lb3_addr <= out_sram1_lb3_addr + 11'd1;
                             r_out_sram1_lb4_addr <= out_sram1_lb4_addr + 11'd1;  end
                                     else begin
                                          r_out_sram1_lb1_addr <= 11'd0;
                                          r_out_sram1_lb2_addr <= 11'd0;
                                          r_out_sram1_lb3_addr <= 11'd0;
                                          r_out_sram1_lb4_addr <= 11'd0;  end                                       
end



//3rd set SRAM
wire out_rd_sram2_pe = xdio_d2 & out_rd_sram2; 
reg [10:0] r_out_sram2_lb1_addr, r_out_sram2_lb2_addr, r_out_sram2_lb3_addr, r_out_sram2_lb4_addr;  
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  begin
     r_out_sram2_lb1_addr <= 11'd0;
     r_out_sram2_lb2_addr <= 11'd0;
     r_out_sram2_lb3_addr <= 11'd0;
     r_out_sram2_lb4_addr <= 11'd0;    
  end else if ( out_rd_sram0_pe ) begin
           r_out_sram2_lb1_addr <= read_out_start;
           r_out_sram2_lb2_addr <= read_out_start;
           r_out_sram2_lb3_addr <= read_out_start;
           r_out_sram2_lb4_addr <= read_out_start;  end
               else if ( data_rvs & out_rd_sram0) begin          //data_rvs=1, out_rd_sram0=1 
                    r_out_sram2_lb1_addr <= out_sram2_lb1_addr - 11'd1;
                    r_out_sram2_lb2_addr <= out_sram2_lb2_addr - 11'd1;
                    r_out_sram2_lb3_addr <= out_sram2_lb3_addr - 11'd1;
                    r_out_sram2_lb4_addr <= out_sram2_lb4_addr - 11'd1;  end
                        else if ( ~data_rvs & out_rd_sram0) begin    //data_rvs=0, out_rd_sram0=1
                             r_out_sram2_lb1_addr <= out_sram2_lb1_addr + 11'd1;
                             r_out_sram2_lb2_addr <= out_sram2_lb2_addr + 11'd1;
                             r_out_sram2_lb3_addr <= out_sram2_lb3_addr + 11'd1;
                             r_out_sram2_lb4_addr <= out_sram2_lb4_addr + 11'd1;  end
                                 else begin
                                      r_out_sram2_lb1_addr <= 11'd0;
                                      r_out_sram2_lb2_addr <= 11'd0;
                                      r_out_sram2_lb3_addr <= 11'd0;
                                      r_out_sram2_lb4_addr <= 11'd0;  end                                       
end



//4th set SRAM
wire out_rd_sram3_pe = xdio_d2 & out_rd_sram3;  
reg [10:0] r_out_sram3_lb1_addr, r_out_sram3_lb2_addr, r_out_sram3_lb3_addr, r_out_sram3_lb4_addr;  
always @(posedge dclk or negedge reset_n)
begin
if (!reset_n)
  begin
     r_out_sram3_lb1_addr <= 11'd0;
     r_out_sram3_lb2_addr <= 11'd0;
     r_out_sram3_lb3_addr <= 11'd0;
     r_out_sram3_lb4_addr <= 11'd0;    
  end else if ( out_rd_sram3_pe ) begin
           r_out_sram3_lb1_addr <= read_out_start;
           r_out_sram3_lb2_addr <= read_out_start;
           r_out_sram3_lb3_addr <= read_out_start;
           r_out_sram3_lb4_addr <= read_out_start;  end
               else if ( data_rvs & out_rd_sram3) begin          //data_rvs=1, out_rd_sram0=1 
                    r_out_sram3_lb1_addr <= out_sram3_lb1_addr - 11'd1;
                    r_out_sram3_lb2_addr <= out_sram3_lb2_addr - 11'd1;
                    r_out_sram3_lb3_addr <= out_sram3_lb3_addr - 11'd1;
                    r_out_sram3_lb4_addr <= out_sram3_lb4_addr - 11'd1;  end
                        else if ( ~data_rvs & out_rd_sram3) begin    //data_rvs=0, out_rd_sram0=1
                             r_out_sram3_lb1_addr <= out_sram3_lb1_addr + 11'd1;
                             r_out_sram3_lb2_addr <= out_sram3_lb2_addr + 11'd1;
                             r_out_sram3_lb3_addr <= out_sram3_lb3_addr + 11'd1;
                             r_out_sram3_lb4_addr <= out_sram3_lb4_addr + 11'd1;  end
                                 else begin
                                      r_out_sram3_lb1_addr <= 11'd0;
                                      r_out_sram3_lb2_addr <= 11'd0;
                                      r_out_sram3_lb3_addr <= 11'd0;
                                      r_out_sram3_lb4_addr <= 11'd0;  end                                       
end



endmodule  
